In mass memory supports, such as for example hard disks, floppy disks, CD, tape streamers and similar devices, digital data are stored by physically recording on the support only the "1", spaced among each other along a magnetic track by segments, the length of which is proportional to the number of "0" present between two successive "1".
Considerations on the dynamic characteristics of revolving or winding supports, impose a minimum distance between adjacent "1". In fact, if any two successive "1" are physically recorded one close to the other on the support, interference between the two recorded "peaks" can cause indetermination and errors during reading due to practical limitations of the discriminating capacity of the reading pick-ups.
Moreover, another peculiarity of these mass storing systems is represented by the fact that the sampling clock signal that is used in the write/read channels circuitry cannot be derived by a system's clock (e.g. by frequency division). Necessarily it has to be a synchronous clock signal that is derived directly from the serial data stream, the "speed" of which may often vary. For example, in the case of a hard disk, data recorded on outer circular tracks may be written and read at a higher speed than data written and read on inner circular tracks. In general, in this as in many other applications, a variable frequency clock signal, synchronous with the serial streams of data, is generated by detecting the succession of transitions of a coded pulse stream that represents a succession of digital data. For example a common phase-locked circuit (PLL), cooperating with a voltage controlled oscillator (VCO), is employed. Where there is the necessity of generating a variable frequency, synchronous time base signal (i.e. synchronous base clock signal), there may be also a practical limit to the maximum "distance" between any two successively recorded "1". Actually, if a transition can occur after an excessively long period of time from a preceding transition, the synchronism of the self-generated clock frequency, "locked" to the pulse stream, can be lost. That could introduce, also in this case, indetermination of the correct sampling instant and therefore errors during reading.
These "dynamic" limitations are commonly overcome by implementing special codification of the data being transferred, capable of ensuring an established minimum number of "0" and an established maximum number of "0" between any successive "1" of a coded binary serial data stream.
Several codifications of this type are known. For example in a so-called Run Length Limited system RLL(2,7), the digits 2 and 7 indicate a minimum number (2) and the maximum number (7), respectively, of "0" between any two "1". In a RLL(1,7) system, the two numbers indicate the minimum number of "0"(in this case 1) and the maximum number of "0" (in this case 7), that may be present between any two successive "1" of a coded binary serial data stream.
Of course, the adoption of a particular coding system of the serial data stream, for example from and to a rotating mass memory support, or also from and to a different type of peripheral having similar dynamic operation characteristics, implies the use of special coding and decoding circuits of the serial stream of digital data.
A common peculiarity of these as well as of other coding/decoding systems is that the "frequency" of the input serial data stream and the "frequency" of the output serial data stream are different. In fact to a certain number X of bits of a decoded serial data, commonly of the so-called NRZ type (an acronym of Non-Return-to-Zero), corresponds a larger number Y of bits of a coded serial data (Y=X+z, z.gtoreq.1). For example, two bits of a decoded NRZ of data signal may correspond to three bits of the coded data signal. This fact implies that during a reading phase, a certain time base frequency (clock) VCO, must be extracted from the sequence of transitions of the coded signal, for example by means of a PLL circuit. The derived VCO signal, synchronous with the incoming serial stream of coded data is employed as clock signal for controlling a shift register to which the coded signal is fed. From said synchronous clock signal fractionary clock signals must then be derived. Suppose, for example, that the ratio between the equivalent number of bits of the coded serial data and of the decoded serial data is equal to 3:2(1.5). From the base clock signal VCO, derived from the transitions of the coded input signal, are derived two fractionary clock signals. A first fractionary frequency clock signal VCO/1.5 is used for sampling the decoded output signal, and a second fractionary frequency clock signal VCO/3 is employed in the timing and synthesizing functions that are performed by the decoding circuitry of the decoder.
For example, in case of an RLL(1,7) code, the decoding and coding tables are shown in FIGS. 1 and 2, respectively.
A common architecture of a decoder is shown in FIG. 3, while the timing diagrams are shown in FIG. 4.
As shown in FIG. 3, a shift register SR receives the serial stream of coded data, SYNDATA, and is synchronized with the extracted base clock signal VCO. It may be provided with a number of flip-flops (FFn) greater than the number of bits handled by the decoder, which for example, in the case shown, is of 7 bits. The flip-flops in excess, relative to the Q0 and Q1 taps of the shift register SR, may be employed for other accessory functions, as is well known to a person skilled in the art. A first combinative logic block RC1 processes the Q outputs of the seven flip-flops Q&lt;2:8&gt;, that is the taps relative to the seven bits handled by the decoder, and produces an output value ND0. That output is fed to a first timing flip-flop A, sampled at the first fractionary frequency clock signal VCO/1.5. The Q output of the flip-flop A is fed to a second combinative logic block RC2, to be combined with the values of the second fractionary frequency clock signal VCO/3 and of a fractionary number of bits (the bits present at the taps Q5, Q6 and Q7 of the respective flip-flops of the shift register SR) of the total number of bits handled by the decoder. The second fractionary frequency clock signal VCO/3 is fed to the second combinative logic block RC2, in order to modify the logic function of the block. As shown in FIG. 3, in this way its output may assume alternatively the value NQ0, as produced by the first combinative block RC1 and timed by the first flip-flop A, or the value produced by RC2 by processing the relative Q5, Q6 and Q7 bits. In practice, RC2 "incorporates" a multiplexer, necessary for bringing to an output stage of the decoder a signal ND1, containing the decoded information, in the form of two decoded bits. The decoded bits are then sampled at the fractionary frequency of the output clock signal VCO/1.5, in order to produce the serial output NRZ data stream. Specifically, a synthesized output value ND 1, produced by the second combinative logic network RC2, is fed to a second output sampling flip-flop B, which is also controlled, as the first flip-flop A, at the first fractionary frequency clock signal VCO/1.5. The output signal of the second flip-flop B represents the decoded NRZ stream having a "frequency" that is different (a fraction thereof) from the "frequency" of the input coded serial data stream.
Generally, the logic functions necessary for decoding (specified in the respective decoding blocks in the figures), are defined as sums of products. They may be implemented with a two-level logic, a first AND level and a successive OR level. In a practical embodiment it is possible to employ two levels of NAND gates because they are notably more efficient in CMOS technology. Of course, logic circuits with more than two levels may also be employed, for implementing different decodings, or for reducing the number of inputs of single logic gates, in case it may become excessively large.
The two decoding combinative logic networks RC1 and RC2 will have a precisely quantifiable delay of propagation, depending on the fabrication technology of the integrated circuit. Such a propagation delay determines the maximum frequency of operation of the decoder. In the example taken into consideration, as visualized in the timing diagrams of FIG. 4, the operative limit of the circuit is given by a maximum "period" corresponding to two times the delay of propagation of the decoding combinative logic networks. This intrinsic speed limit of the circuit derives from the fact that alternatively each of the two combinative logic networks RC1 and RC2 must complete its function (obviously with the propagation delay of the network) within a half-period of the extracted synchronous clock signal VCO. This limiting aspect is indicated by the arrows and labels placed on the timing diagrams of the circuit shown in FIG. 4.
This mechanism of limitation of the maximum operating frequency imposed by the fabrication technology used for realizing the decoding combinative logic networks, is intrinsic to decoders of the type in question, irrespectively of the particular coding that is used.